Primitive Delay Faults: Identi cation, Testing and Design for Testability

We investigate two strategies to guarantee temporal correctness of a combinational circuit. We rst propose a new technique to identify and test primitive faults. A primitive fault is a path delay fault that has to be tested to guarantee the performance of the circuit. Primitive faults can consist of single or multiple path delay faults. Testing strategies for single primitive faults exist. In this paper, we focus on identifying and testing multiple primitive faults. Identiication and testing of these faults is important for at least two reasons: (1) a large percentage of paths in production circuits remain untestable under the single-path delay fault model, and (2) distributed manufacturing defects usually adversely aaect more than one path and these defects can be detected only by analyzing multiple aaected paths. The single-path delay faults contained in a multiple primitive fault have to merge at some gate(s). Our methodology can quickly (1) rule out a large number of gates as possible merging gates for primitive faults, and (2) prune the combinations of paths that can never belong to any primitive fault. Our identiication procedure also nds a test for the fault. We present a complete algorithm for identifying and testing double path delay faults. Identifying and testing all primitive faults is impractical for large designs. This is because no eecient methods are known for testing primitive faults that include a large number of paths. However, to guarantee that the performance of a digital circuit is not aaected by timing defects, it is necessary to test all primitive faults. Our second contribution is a new design for testability method. Our method guarantees that only primitive faults with at most two paths can exist in the circuit in the test mode. The main idea is to eeciently identify a small set of signals for inserting test points to eliminate primitive faults with more than two paths. Our test points only provide controllability. Addition of a single test point can lower the cardinality of several primitive faults. Our approach eeciently re-evaluates primitive delay fault testability of the circuit after insertion of a test point. After a few iterations only primitive faults with at most two paths can exist in the circuit in the test mode. Experimental results on several multi-level combinational benchmark circuits are included to demonstrate the usefulness of our techniques. Fig. 1. Classiication of path delay faults. Fig. 2. Delay distribution for s1269 for …